NDS Emulator
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About ensata NITRO Software Emulator
System Requirements
Compatibility with NITRO
ensata NITRO Software Emulator Basic Operations
Basic Operation
Opening Files
Game Screen Operation
Debug Output Console
RTC Settings
Backup Memory
Setup/Save NITRO Software
ensata NITRO Software Emulator Applied Operations
Modifying the Separator Panel Skin
Main Memory Capacity Settings

ensata NITRO Software Emulator

NDS ROMs Compatibility with NITRO
Implementation Status of ensata NITRO Software Emulator

Items with no entry have been implemented.
  • ARM 946ES
    • CP15
      • Register1 TBIT Load Specification Control -  Not implemented (normally set to enable)
      • Register1 Cache Substitution Algorithm -  Not implemented (implemented only for Round-Robin)
      • Register13 Trace Process Identifier Register -  No plans for implementation
      • Register15 -  No plans for implementation
    • CPU
      • LDC, STC, CDP Instructions -  Not implemented
  • Memory
    • NITRO Game Card -  Not implemented
    • AGB Game Pak -  Not implemented
    • Shared Work RAM -  Not implemented
  • Display
    • Forced Blank -  Not implemented

  • 3D Graphics
    • Geometry
      • Geometry engine processes are implemented with a process time of zero.
      • Coordinate values during calculation overflow differ greatly from the production unit.
      • Counter values for Polygon List RAM/Vertex RAM overflow do not update (updates will occur on the production unit)
      • Specifications for polygon auto sort on the Nintendo DS system is not implemented
    • Software Rendering
      • All features implemented. (However, differences in the image may exist.)
    • D3D Rendering
      • The attribute buffer is not emulated.
        • The fog enable flag and Polygon ID (translucent and opaque) are disabled.
      • The fog enable flag for clear register is disabled.
      • When the video board's W buffering cannot be used, Z buffering can be used when W buffering.
      • Initialization with clear image is allowable with a video board that supports Pixel Shader 2.0 or greater. However, if the video board does not support W buffering, initialization is not allowed when using W buffering.
      • Quadrilateral Polygon
        • Quadrilateral polygons are rendered as triangles.
          For this reason, when the four vertices are not on the sample plane, the display will vary on the production unit. Also, the same limitations apply to the vertex color. However, this type of quadrilateral polygons may not display correctly on the production unit, so they should be avoided.
      • Translucent Polygon
        • The feature that prevents overwriting when polygons with the same Polygon ID overlap is not emulated.
        • The software emulator does not emulate the specification that calls for including in attributes the result from an AND operation performed on the fragment fog enable flag and the attribute buffer fog enable flag.
      • Shadow Polygon
        • When rendering shadow polygons, the software emulator does not emulate the specification that calls for rendering only when the opaque attribute Polygon ID differs from the translucent Polygon ID of the rendering shadow polygon. Therefore, the object that casts a shadow may cast a shadow on itself.
        • Fog color is combined with the vertex color using the fragment fog enable flag.
        • A rendering shadow polgon may be displayed due to discrepancies in precision.
        • Mask does not function on video boards that do not support stencils.
      • Texture
        • Decal Mode
          • Exception processing when At=0 or At=31 is not emulated. For this reason, the coloring may occasionally differ.
      • a-Blending
        • The output a value is also blended using the a value. (max[As,Ab] on the production unit)
        • Exception processes are not emulated.
          • For this reason, even if the color buffer a value is zero (Ab=0), a-blending is performed using the fragment a value. On the production unit, when the color buffer a is zero (Ab=0), if the fragment a value is not zero, then the color is rendered as is and may be opaque on the screen.
        • When a-blending is set to OFF with DISP3DCNT, polygons may not be displayed properly.
      • Edge Marking
        • Due to limitations in implementation, the edge marking line may break in the middle.
        • Edges may be displayed at the intersection of polygons.
        • Edges may be displayed where extracted portions and neighboring opaque portions meet.
      • Fog
        • Because fog color is combined with vertex color before rendering, the results may differ from the production unit.
      • Anti-Aliasing
        • Not emulated.
  • Timer
    • Prescaler selection is the one cycle of the timer count value -  Not implemented
  • Interrupt
    • Geometry Command FIFO Interrupt -  Not implemented
    • NITRO Game Card IREQ_MC Interrupt -  Not implemented
    • NITRO Game Card Data Transfer Completion Interrupt -  Not implemented
    • ARM9/7FIFO Not Empty Interrupt -  Not implemented
    • ARM9/7FIFO Empty Interrupt -  Not implemented
    • ARM7 Interrupt -  Not implemented
    • Game Pak Interrupt -  Not implemented
  • Sub Processor (ARM7)
    • No plans to implement at hardware level (software patch)

Copyright (C) 2004 Nintendo

Download Ensata 1.3c - ensata NDS ROMS - Nintendo DS emulator Ensata